With the development of a chip integration trend, more and more chips need to use an internal high-speed bus (bus) to exchange data. With the development of a multi-core trend and increase of functions integrated on a chip, complexity of the internal high-speed bus of the chip is increasingly high. However, a complex bus is faced with an increasingly high probability of problems. How to debug the bus and locate the problems is always a main issue troubling the front-end design of the chip, EDA/FPGA/Emulator verification, and chip software development and debugging.
At present, the high-speed bus protocol in the chip is generally based on multi-channel processing. For example, an AXI (Advanced Extensible Interface) bus of the ARM (Advanced RISC Machines) Holdings company has five channels, namely, a read address channel (AR), a write address channel (AW), a write data channel (W), a read data channel (R), and a write response channel (B).
FIG. 1 is a schematic diagram of a master device (Master) and a slave device (Slave) that are connected by a high-speed bus (BUS) in the prior art. As shown in FIG. 1, a high-speed bus 13 between a master device 11 and a slave device 12 has five channels, namely, a read address channel (Read Address Channel) 14, a read data channel (Read Data Channel) 15, a write address channel (Write Address Channel) 16, a write data channel (Write Data Channel) 17, and a write response channel (Write Resp Channel) 18. The master device 11 is defined as an active initiator of a command and data writing and a receiver of a returned response, while the slave device 12 is defined as a receiver of the command and an initiator of data reading and the response. Generally, a processor is used as the master device 11, and has a master port connected and used with a master port of the high-speed bus 13 to actively read data; and a memory (memory) is used as a slave device 12, and has a slave port connected and used with a slave port of the high-speed bus 13 for the master device 11 to read data and return a response.
FIG. 2 is a time sequence diagram of each channel in a high-speed bus shown in FIG. 1. As shown in FIG. 2, each channel uses a full handshake mechanism, that is, when no ready pulse arrives, a valid pulse is not revoked and a next command cannot be sent.
FIG. 3 is a schematic diagram of an existing system on chip SoC (System on Chip). As shown in FIG. 3, a system on chip 30 includes multiple master devices (master) 31, multiple slave devices (slave) 32, and even multiple high-speed buses (Bus) 33. In FIG. 3, the arrow direction indicating the output direction indicates the command output of a master device 31, and the arrow direction indicating the input direction indicates command receiving of a slave device 32. Each arrow direction corresponds to five channels of a high-speed bus. Because the high-speed bus 33 interconnects all master devices 31 and all slave devices 32, all the master devices 31 can access all the slave devices 32. If any node of the high-speed bus, for example, any master device, slave device, or any one or more channels in ports of the bus, is faulty, the fault spreads to a plurality of nodes. That is to say, as long as an operation passes through the faulty node, the operation cannot be completed. Therefore, as long as a node is faulty, the whole system may be affected, so that the whole system on chip is in a deadlock state.
When the deadlock state occurs, all tasks are stopped. However, as the scale of the system on chip is increasingly large and the bus interconnection is increasingly complex, the above problem is more obvious. In addition, generally the high-speed bus may send multiple uncompleted commands at a time, and support disordered return of commands. This further increases the difficulty in locating the faulty node.
At present, the industry has developed a high-speed bus monitoring technology to solve the above problem. At present, the main principle of a known bus monitoring technology lies in: recording all behaviors of nodes on the high-speed bus, then forming a data stream by packetization and decompression, and sending the data stream to a buffer in the system on chip for storage, or sending the data stream to a storage module outside the chip for storage through a port of the system on chip. The function is generally called a trace (Trace) method in the industry, and is similar to that an oscilloscope performs signal sampling and storage and then recovers the signal for analysis by debugging personnel.
Generally, a large chip company in the industry uses a bus debug system developed by itself, including a tool chain, and so on. However, as products of the ARM Holdings company are widely used, the Coresight debug component and system that are defined by the ARM Holdings company are gradually used by many companies. The ARM Holdings company has developed a debug component for the highest-speed AXI high-speed bus recently.
FIG. 4 is a schematic diagram of a system on chip using a bus debug technology of the ARM Holdings company in the prior art. As shown in FIG. 4, a system on chip 40 includes an ARM processor core (ARM core) 41, a direct memory access module (Direct Memory Access, DMA) 42, a digital signal processor core (DSP core) 43, a double data rate synchronous dynamic random access memory controller (DDR SDRAM controller) 44, an internal static random access memory (Internal SRAM) 45, and other peripherals (Other Peripheral) 46.
The ARM processor core 41, memory content direct removing module 42, and digital signal processor core 43 are used as master devices (Master), while the double data rate synchronous dynamic random access memory controller 44, internal static random access memory 45, and other peripherals 46 are used as slave devices (slave). The master devices and slave devices are connected through an AXI high-speed bus 47. In addition, a bus trace (BusTrace) apparatus 48 may be arranged at ports connecting the AXI high-speed bus 47 and the master devices and slave devices, so as to record each command passing through the ports. The bus trace apparatus 48 may be arranged at some ports of the AXI high-speed bus 47 as required to connect to the master devices or slave devices. Herein the bus trace apparatus 48 is arranged at ports of the AXI high-speed bus 47 connecting the ARM processor core 41, memory content direct removing module 42, digital signal processor core 43, double data rate synchronous dynamic random access memory controller 44, and internal static random access memory 45.
When the system on chip works, the bus trace apparatus 48 is used as a debug component, which records events such as command sending and response returning of a port corresponding to the AXI high-speed bus 47, forms a frame in a format by using an event content, and incorporates a unique ID assigned by each bus trace apparatus 48 as an identifier into the frame. Then, the recorded content is output through a debug bus 49. The debug bus 49 may be an ATB debug bus defined by the ARM Holdings company, and is independent of the AXI high-speed bus 47. Then, through the ATB debug bus 49, relevant information of each port of the AXI high-speed bus 47 is finally stored in a buffer (buffer) in the system on chip 40, or stored in a DDR memory outside the chip, or output to the outside of the chip through a high-speed port (High Speed I/O).
Test personnel may read the buffer in the system on chip or the DDR memory outside the chip through the tool chain provided by ARM, so as to read the stored content, and by parsing an ID and a frame format of each bus trace apparatus 48, recover the relevant information of a corresponding port of the AXI high-speed bus 47, which is recorded by a corresponding bus trace apparatus 48 within a period.
The above bus debug technology of the ARM Holdings company does not support real-time locating of problems in principle, but belongs to an after-event passive system. After other problems occur in the running of the system on chip, test personnel may query a history record exported by the bus trace apparatus 48, and perform after-event analysis to locate the problems, where the workload of and requirement for analyzing and locating are higher.
In addition, because there is limited storage space corresponding to the bus trace apparatus 48, use of the above debug technology generally requires that one or more trigger conditions of an adjacent time point of a problem should be found, so as to trigger the starting or stopping of trace, or that a filter condition should be found, so that the bus trace apparatus 48 records only behaviors of the bus in the case that a special condition is satisfied. However, searching of the trigger condition or filter condition needs to be analyzed manually and set; and if the setting is incorrect, behaviors of the adjacent time point of the problem may be not recorded; as a result, a problem scenario needs to reoccur repeatedly. Therefore, the debug efficiency is lower.
An existing trace-based bus monitoring technology does not support anomaly recovery in principle, and only records a problem which occurs, and then subsequently provides the record for the test personnel to perform after-event analysis.
In addition, the above bus debug technology exports and stores the behavior events in real time. Because an operation of the bus is generally fast, there are many events within a period. To record enough information within a period and ensure that the information is not lost, the bus debug technology has a certain requirement and cost for the storage space and bus performance.
If the event content is stored in the system on chip, the buffer of the system on chip requires enough space and its power consumption cost is correspondingly increased.
If the event content is stored in the DDR memory outside the chip, the event content needs to occupy port traffic of the DDR memory. However, when bus events frequently occur, generally the bus frequently accesses the DDR memory, which may generally require the bandwidth of the DDR memory to synchronously increase and change, and therefore, has a great impact on the system performance.
If the event content is exported to the outside of the chip through a high-speed port, a high requirement is imposed on a PAD type selection and printed circuit board PCB design, and hardware outside the chip needs to be purchased from the ARM Holdings company. Therefore, the cost is high.
In addition, the bus debug technology of the ARM Holdings company needs to be supported by the tool chain of the ARM Holdings company, cannot support self-locating of new trace contents, and is inflexible.
At present, a bus debug technology developed by the TI (Texas Instruments, Texas instruments) Incorporated company is also popular in the industry, and the bus trace technology is basically similar to that of the ARM Holdings company, with the only difference in that: In the bus debug technology of the TI company, an input event may come from a VBUSM high-speed bus of the TI Incorporated company instead of the AXI high-speed bus of the ARM Holdings company, and a bus for exporting the record content of the bus trace apparatus to the buffer is a VBUSP test bus of the TI Incorporated company instead of the ATB test bus of the ARM Holdings company. In addition, the bus debug technology of the TI Incorporated company supports only importing the content output by the bus trace apparatus to the buffer in the system on chip, but does not support importing the content output by the bus trace apparatus to the DDR memory outside the chip or using a high-speed port to export the content to the outside of the chip.
The bus debug technology of the TI Incorporated company has the same disadvantages as the bus debug technology of the ARM Holdings company, and because it does not support importing the content output by the bus trace apparatus to the DDR memory outside the chip or using the high-speed port to export the content to the outside of the chip, the bus debug technology of the TI Incorporated company has a greater impact on the cost of the power consumption on chip than the bus debug technology of the ARM Holdings company.
Therefore, how to quickly locate and restore the faulty node of the high-speed bus is one of urgent problems to be solved.